Currently, due to development of semiconductor fabrication technologies and integrated circuit design technologies, an integrated circuit system is mainly designed with a System-On-Chip (SoC) which integrates all components of a system into one chip.
As the semiconductor fabrication technologies and the integrated circuit design technologies have recently been further developed, the number of devices, which can be integrated into one chip, is increased gradually. Due to this trend, a wiring structure of transmission lines designed in one chip becomes complex. Accordingly, if the integrated circuit system is realized with a SoC design method, the number and lengths of transmission lines and the signal delay caused due to interference therebetween are very important design parameters that should be considered for normal operations of an entire chip.
In another case, if a synchronous design method using a global clock is applied to an integrated circuit system realized with the SoC design method, there occur clock skew and jitter due to the increase of a clock speed and also transmission delay of data due to the increase of the number and lengths of transmission lines. These limitations may be resolved by applying an asynchronous design method to the integrated circuit system realized with the SoC design method.
The asynchronous design method performs data transmission through a Delay Insensitive (DI) data transmitting method that does not use a global clock and supports a handshake protocol that is irrelevant to a delay time. Therefore, the above-mentioned limitations due to the synchronous design method can be resolved. However, according to this asynchronous design method, designing an entire circuit becomes complex and also a Computer Aided Design (CAD) tool used for this asynchronous design method is not sufficiently provided.
As a proposal that may simultaneously resolve the limitations of the synchronous and asynchronous design methods, researches for a Globally Asynchronous Locally Synchronous (GALS) system are actively under development lately.
The GALS system includes a plurality of Locally Synchronous (LS) modules that basically do not use a global clock and operate by independent clocks. Data transmission between the LS modules is completed through an asynchronous handshake protocol.
That is, since the GALS system does not use a global clock, the limitations such as the above mentioned clock skew and jitter are resolved. Since data transmission is completed between the LS modules that operate by different timings through the DI data transmitting method, its stability can be achieved.
In the DI data transmitting method, data are represented through a data encoding method such as dual-rail and 1-of-4. A 4-phase handshaking protocol similar to a related art synchronous design method is used for the DI data transmitting method.
In the 4-phase handshaking protocol, data are basically represented with a binary value of a Return to Zero (RZ) type. That is, according to the 4-phase handshaking protocol, there exists a space state for distinguishing continuous data. Since the space state has the same latency as data, a 2-phase handshaking protocol method having no space state is more effective than the 4-phase handshaking protocol method in the GALS system where data transmission occurs frequently.
According to the 2-phase handshaking protocol based on a dual-rail, which is known as a Level-Encoded 2-phase Dual-Rail (LEDR), its one wire is encoded with data and the other wire is encoded with a phase change. This is different from a related art dual-rail based 2-phase protocol that encodes data transmission of 0 and 1 with state changes of the respective two wires. That is, data of 0 and 1 are encoded with a level not a state change in one wire, and distinction between data is accomplished with a change of the other wire.
As a result, an XOR value of the two wires is changed according to each data transmission and this is detected to determine effectiveness of data. Since there is no necessary for decoding data, compared to the related art dual-rail based 2-phase protocol, performance of the dual-rail based 2-phase handshaking protocol becomes higher and its design complexity becomes less. However, since the 2N+1 number of wires is required for N-bit data transmission, performance, power consumption, and design complexity of the dual-rail based 2-phase handshaking protocol become disadvantageous by the increased number of wires.
In “signal transmitting and receiving device for a new wiring system disclosed in Korean Patent Application No. 1997-018460, several different kinds of signals are simultaneously transmitted through one wire between a plurality of function blocks in an integrated circuit. Thus, a single transmitting and receiving device for a new wiring system, which is capable of reducing its area that wiring occupies, can be provided. Theoretically, while N-bit data are transmitted, the 2^N number of voltage values having a triangle pulse shape is encoded and transmitted through one wire and then, a receiver circuit detects this and restores the transmitted N-bit data. Therefore, the number of wires necessary for wiring is decreased and an overall area of an integrated circuit is reduced. However, as the number of voltage values that can be encoded in a wire is increased, the number of logic to be decoded is increased. As a result, complexity of a receiver circuit becomes increased more and thus there occur limitations in reducing the number of wires. Since the tendency is toward lowering a supply voltage in an integrated circuit, a multiple valued logic circuit technique using a voltage that this invention uses may deteriorate a noise margin characteristic of a voltage in a receiver circuit. Additionally, since a function for providing a handshake protocol necessary for DI transmission is not provided, the multiple valued logic circuit technique cannot be applied to the GALS systems.
Various protocols for supporting DI transmission and applying a ternary encoding method to reduce the number of wires have been studied.
In “Delay-insensitive data transfer circuit using current-mode multiple-valued logic” disclosed in U.S. Pat. No. 7,282,946, a noise margin of a supply voltage is not affected through a multiple valued logic of a current mode method and three logic states can be represented in one wire. Therefore, circuit design having N+1 wires can be used for N-bit data transmission.
In “Delay insensitive data transfer apparatus with low power consumption” disclosed in U.S. Patent Publication No. 20080123765, a high constant current consumption characteristic occurring in the related art DI data transmitting method using a current mode is complemented and thus power consumption in a standby state is drastically reduced.
However, since the DI data transmitting method using the above-mentioned two kinds of current mode circuits is fundamentally based on a 4-phase data transmitting method, its performance is theoretically reduced to the half, compared to a 2-phase DI data transmitting method such as LEDR.